The present invention relates to a semiconductor device having electrode terminals arranged at a very fine pitch and a method for manufacturing the same.
In the technique of mounting a semiconductor chip, such as an LSI, called a chip size package (CSP) for instance, the semiconductor chip is mounted by a sub-circuit board to a circuit board (main circuit board), not directly on the main circuit board. In order to readily connect very fine electrode terminals of the semiconductor chip to an external electric circuit, the sub-circuit board is mounted between the semiconductor chip and the external electric circuit with the use of solder bumps provided at a wider pitch than the width between the adjacent electrode terminals of the semiconductor chip and each having a contact area greater than that of the electrode terminals of the semiconductor chip. FIG. 18 shows one form of a conventional such semiconductor device (an integral structure of a semiconductor chip and sub-circuit board). A plurality of circular holes 2 are provided in a matrix-like pattern in the substantially whole surface of a film board 1, such as polyimide, constituting the sub-circuit board. A plurality of first connection electrodes 3 are so provided on the lower surface of the film board 1 that they are plated with gold to close the respective circular holes. The plurality of first connection electrodes are electrically connected to corresponding second connection electrodes 4, respectively by corresponding interconnect lines 5.
A semiconductor chip 11 has a silicon substrate 12 covered with a protective layer 14 exposing a plurality of connection electrode terminals 13 on the silicon substrate 12.
The plurality of connection electrode terminals 13 are arranged at the upper circumferential edge portion of the silicon substrate 12 in a spaced-apart relation. The protective layer 14 of a silicon oxide or silicon nitride is formed on the whole upper surface of the silicon substrate 12 except at the central areas of the respective connection electrode terminals 13. The central areas of the connection electrode terminals 13 are exposed at the corresponding openings 15 in the protective layer 14.
The joining together of the sub-circuit board and semiconductor chip 11 will be explained below.
First, the sub-circuit board is bonded by an elastic adhesive agent 16 to the upper central area of the protective layer 14 of the semiconductor chip 11. As shown in FIG. 19, since the exposed areas of the connection terminals 13 are formed at a pitch LP which is very narrow, those second connection electrodes 4' to be connected are bent, while being depressed by a bonding tool 18 one by one, into contact with the corresponding connection electrode terminal 13 in a single point thermosonic bonding process. By the heating of the bonding tool 18, a gold-plated area melted at the surface of the second connection electrode 4 of the sub-circuit board is soon solidified to achieve a bond between the second connection electrode 4 and the connection electrode terminal 13 and hence an electrical connection between both. The pitch LP, width TW of the bonding tool 18 as viewed along the width direction of the connection electrode 4, and width LW of the connection electrode are of the order of 65 to 100 .mu.m, 70 to 100 .mu.m and 30 to 50 .mu.m, respectively. The joined areas are sealed later with the resin sealing material 17 and a substantially spherical solder bump 6 is provided on the exposed areas in the circular hole 2 in the first connection electrode 3.
In the conventional such semiconductor device, use is made, as the sub-circuit board, of a 50 to 125 .mu.m-thick film board 1 which is an additional component unit. And the film board 1 is bonded by a 50 to 100 .mu.m-thick elastic adhesive layer 16 to the upper surface of the protective layer 14 on the semiconductor chip 11 so as to ensure adequate bondability. A resultant structure becomes considerably thicker as a whole, thus posing a problem. The elastic adhesive layer 16 has to be thickened to a given extent so as to absorb physical stress and suppress the deformation of the sub-circuit board and semiconductor chip 11. Further, the thickening of the second connection electrode 4 causes the extent of its bending to be increased at a time of a thermobonding step, so that it is vulnerable to a breakage. Also, since the second connection electrode 4 of the film board 1 is bonded to the connection electrode terminal 13 of the semiconductor chip 11, checking has to be made to see whether or not any positive bond is ensured at that area. This leads to a time-consuming problem. The second connection electrodes 4 are very fine and narrow in their pitch and, moreover, the greater in number of the second connection electrodes the lower in their throughput.
The semiconductor chip 11 has an area of its bond to the sub-circuit board exposed at its side wall and, through mechanical stress involved, a clearance is liable to be created between the protective layer 14 and the silicon substrate 12 or between the protective layer 14 and the resin sealing material 17. As a result, a moisture penetrates through the clearance and there sometimes occurs a poor conduction or conduction failure.
An object of the present invention is to provide a semiconductor device, and method for manufacturing the same, which can be made thinner as a whole without the need for providing a sub-circuit board and ensure a better yield in productivity.
Another object of the present invention is to provide a semiconductor device of better electrical performance.